With an increase in the integration level of semiconductor integrated circuits (ICs), the width of metal interconnection lines generally decreases. Additionally, the aspect ratio (the ratio of depth to width) of a contact hole or via generally continues to increase because a proportionate decrease in contact depth is typically not realized with the decrease in interconnection metal width. With the increase in aspect ratio, aluminum (Al) alloy films currently used as the material for metal wiring may show poor step coverage in a contact hole or may have a void in the contact hole resulting from the sputter-formation of the Al. As a result of these possible limitations of Al, an open may occur between metal interconnection lines which lowers the reliability of the IC.
Recently, in light of the limitations of Al as an interconnect metal, the use of tungsten (W) as an interconnect material has attracted attention. FIGS. 1A through 1E illustrate a method for forming a tungsten layer by chemical vapor deposition (CVD).
In FIG. 1A, an impurity region 12 which defines a source/drain region is formed by implanting ions into a silicon substrate 10. Then, a silicon oxide layer is formed as an insulating layer 13 to a thickness of 500-2000 .ANG. on the overall surface of the substrate 10 including the impurity region 12. As shown in FIG. 1B, a trench 19 for forming a metal wiring therein is formed by etching the insulating layer 13 and the silicon substrate 10 to a predetermined depth.
Subsequently, a titanium (Ti) layer is deposited to a thickness of 200-1500 .ANG. on the insulating layer 13 and in the trench 19 and then thermally treated. As a result of the thermal treatment, the silicon substrate 10 reacts with the Ti layer to form a titanium silicide (TiSi.sub.x) layer 14. The titanium silicide layer acts as an ohmic layer on the contact surface with the substrate. The remaining Ti which did not react with the substrate is removed by wet etching which results in the configuration shown in FIG. 1C.
As shown in FIG. 1D, after etching, a titanium nitride (TiN) layer is deposited as a diffusion-barrier layer 15 to a thickness of 150-900 .ANG. and a tungsten layer 16 is deposited on the diffusion-barrier layer 15 to a thickness of 1000 .ANG. or more. After deposition, the diffusion-barrier layer and the tungsten layer are etched back by chemical mechanical polishing (CMP) so that the tungsten layer 16 remains only in the trench 19 as shown in FIG. 1E, thus, completing the metal wiring.
One difficulty which may arise as a result of the structure described above results from the differing physical characteristics of the materials which make up the SCVD-W metal wiring. When metal wiring is formed by SCVD-W, the TiN layer, which acts as a diffusion-barrier layer, has physical properties, for example, tensile force, which differ from those of the W layer used as the metal wiring layer. Thus, the interface between the TiN and W layers may be highly stressed. Consequently, the tungsten layer may lift from the adjacent layers or the TiN layer/W layer may lift from the insulation layer during CMP or other processing steps in which physical force is applied to the structure. This lifting may cause a loss of contact between the layers and result in an undesired open electrical condition in the wiring.
Another possible difficulty with the above structure may arise, when the impurity region is formed using boron (B) as a P.sup.+ impurity. In such a case, the impurity may react with Ti in a subsequent thermal process, thus forming TiB.sub.2. As a result, the ohmic contact characteristics may be degraded which may cause the contact resistance to increase.
To overcome the above problem, a method as shown in FIG. 2A has been suggested in which a tungsten layer 24 is formed as an ohmic layer and a tungsten nitride layer 25 as a diffusion-barrier layer on an impurity area 22 formed on a silicon substrate 20. A tungsten layer 26 is then formed as a metal wiring layer. In such a method, the tungsten layer 24, which acts as an ohmic layer, is formed to a thickness of 200-1500 .ANG. by flowing tungsten fluoride (WF.sub.6) at 6 sccm and hydrogen (H.sub.2) at 200 sccm, respectively, at a deposition temperature of 6000.degree. C. under a pressure of 0.1 Torr. Then, the tungsten nitride layer 25, which acts as a diffusion-barrier layer, is deposited to a thickness of 150-900 .ANG.. Then a tungsten layer 26 is deposited to a thickness of 1000 .ANG. or more on the tungsten nitride layer 25. The layers are then etched back to complete the metal wiring.
A section of the metal wiring is shown in a scanning electron microscopy (SEM) photo of FIG. 2B. While the tungsten layer formed as an ohmic layer shows excellent adhesion to silicon, the reduction reaction of tungsten with silicon forms tungsten silicide which leads to encroachment on the silicon substrate and can lead to deterioration of the electrical characteristics the device. Encroachment on the substrate may become an even more serious problem in the ULSI era when junction depth is decreased to 0.1 .mu.m or below. Furthermore, since tungsten reacts with Si at 550.degree. C. or above, it is difficult to apply the above described metal wiring fabrication method to a fabrication process of a semiconductor device if a subsequent step of the fabrication process must be performed at a temperature higher than 550.degree. C. In view of these limitations, improvements are needed in methods of fabricating tungsten-based interconnections and wiring.